1. Field of the Invention
The present invention generally relates to a fuse circuit, and more specifically, to a technology of reducing current consumption by reducing peak current in a reset mode of a fuse circuit used for analysis and repair of memory design.
2. Description of the Prior Art
Generally, a fuse circuit has been widely used for analysis and repair of memory design.
FIG. 1 is a diagram of a conventional fuse circuit.
The conventional fuse circuit comprises enable fuse units EF1 and EF2, fuse sets 10 and 20 each corresponding to the enable fuse units EF1 and EF2. The fuse sets 10 and 20 comprise a plurality of fuse units F0˜F11. If the enable fuse units EF1 and EF2 are activated, the conventional fuse circuit operates the plurality of fuse units F0˜F11 to store address information of defect cells.
FIG. 2 is a circuit diagram of the enable fuse units EF1 and EF2 or a plurality of fuse units F0˜F11.
The enable fuse units EF1 and EF2 or the plurality of fuse units F0˜F11 comprise a fuse f1, NMOS transistors N1˜N3, and inverters IV1 and IV2.
The fuse f1 is connected between a power voltage terminal VDD and the NMOS transistor N1. The NMOS transistor N1 connected between the fuse f1 and the NMOS transistor N2 has its gate to receive a reset signal RESET.
The NMOS transistor N2, a constant-current device which is connected between the NMOS transistor N1 and a ground voltage terminal, receives a power voltage VDD at its gate and is always turned on.
The inverters IV1 and IV2, connected serially, buffer an output signal from the common node of the fuse f1 and the NMOS transistor N1.
The NMOS transistor N3 has a drain connected to an input terminal of the inverter IV1, a source connected to the ground voltage terminal and a gate to receive an output signal from the inverter IV1. Here, if the NMOS transistor N3 is turned on by the output signal from the inverter IV1, the NMOS transistor N3 precharges the input terminal of the inverter IV1.
The above-described conventional fuse unit checks through the reset signal RESET whether the fuse f1 is turned on or off.
If the NMOS transistor N1 receives the reset signal RESET as a pulse type, the NMOS transistor N1 is turned on and penetration-current IDD flows. The NMOS transistor N2 is continuously kept on because the power voltage VDD is applied to the gate of the NMOS transistor N2.
When the NMOS transistor N1 is turned on, a high level signal is applied to a node NO1 if the fuse f1 is connected, and a low level signal is applied to a node NO1 if the fuse f1 is disconnected.
In this way, the conventional fuse circuit performs a reset operation to check whether the fuse f1 is turned on or off. But, if the reset signal RESET is activated, the conventional fuse circuit operates the fuse sets 10 and 20 at the same time regardless of whether the fuse sets 10 and 20 are used or not so that a large amount of the peak current generated instantly flows.
As a result, the conventional fuse circuit requires a large amount of current when the reset operation of the fuse circuit is performed, and the generated peak current causes power noise of the fuse, thereby destabilizing the operation of the fuse circuit.